Low-cost and efficient prediction hardware for tabular data using tiny classifier circuits
Published in Nature Electronics, 2024
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Publications
Exploring Sparse Visual Odometry Acceleration on FPGA with High-level Synthesis.
Published in IEEE Access, 2023
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Tiny Classifier Circuits: Evolving Accelerators for Tabular Data.
Published in ArXiv, 2023
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Loopapalooza: Investigating Limits of Loop-Level Parallelism with a Compiler-Driven Approach.
Published in 2021 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2021
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Analysis of the Usage Models of System Memory Management Unit in Accelerator-attached Translation Units.
Published in MEMSYS 2020: The International Symposium on Memory Systems, 2020
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DBHI: A Tool for Decoupled Functional Hardware-Software Co-Design on SoCs.
Published in Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020
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SimAcc: A Configurable Cycle-Accurate Simulator for Customized Accelerators on CPU-FPGAs SoCs.
Published in 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2019
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A performance evaluation of multi-FPGA architectures for computations of information transfer.
Published in Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, 2018
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