DBHI: A Tool for Decoupled Functional Hardware-Software Co-Design on SoCs.
Published in Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020
This paper presents a system-level co-simulation and co-verification workflow to ease the transition from a software-only procedure, executed in a General Purpose processor, to the integration of a custom hardware accelerator developed in a Hardware Description Language (HDL).
We propose a tool which enables Dynamic Binary Modification to decouple the development of the hardware accelerator from the software-only application to be accelerated. It provides support for rapid iterative exploration and functional verification of hardware designs while keeping the unmodified software application as a reference. DBHI is able to instrument an application and inject compiled hardware. It allows progressive migration from application source code, to non-synthesizable HDL, and to synthesizable HDL. At the same time, it preserves cycle-accurate/bit-accurate results, and provides run-time visibility of the internal data buffers for debugging purposes. Foreign architecture emulation overhead during development is avoided, and early integration with peripherals in the target System-on-Chip is possible.
The proposed design flow was evaluated on executions of hardware simulations on x86-64 and Arm. DBHI was developed from existing off-the-shelf tools, and we evaluated it on multiple architectures, however, the technique is not tied to any specific architecture.