I am a Senior ASIC Design Engineer at Pragmatic Semiconductor, where I work on pioneering projects that push the limits of flexible IC technology. Previously, I was a Research Associate at The University of Manchester. I hold an MEng in Electrical and Computer Engineering from the Technical University of Crete and a PhD in Computer Science from The University of Manchester.

My PhD research focused on two primary areas: (a) understanding the interaction of specialised compute kernels with processors in modern systems and their impact on overall system performance, and (b) designing Machine Learning accelerators for the classification of tabular data using evolutionary algorithms. This work involved their fabrication on flexible substrates, and implementation on ASIC and FPGAs.

During my PhD, I spent nine months at Arm Research in Cambridge, where I worked on parallelism at the loop level by studying the effects of various parallelization strategies, constraints, and data dependencies across loops.

I live, work and travel under the influence of music..

News

• April 2024: Our paper “Low-cost and efficient prediction hardware for tabular data using tiny classifier circuits” is available in Nature Electronics website.

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